000 00525nam a2200181Ia 4500
008 221221s9999 xx 000 0 und d
020 _a9780070252219
041 _aENG
082 _a621.392
_bNAV/V
100 _aNavabi, Zainalabedin
245 0 _aVerilog Digital System Design
_bRt Level Synthesis, Testbench And Verification
250 _a2
260 _aNew Delhi
_bTata Mc Graw_Hill
_c2006
300 _a384
_eC D Included
650 _aElectronics & Communication
650 _aVerilog Digital System
942 _cBK
999 _c34057
_d34057