St. Joseph’s College of Engineering and Technology, Palai

Choondacherry P.O, Palai, Kottayam 686 579, Kerala, India.

Library and Information Division

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Verilog Digital System Design Rt Level Synthesis, Testbench And Verification

Navabi, Zainalabedin

Verilog Digital System Design Rt Level Synthesis, Testbench And Verification - New Delhi Tata Mc Graw_Hill 2006 - 384

ISBN: 9780070252219

Subjects--Topical Terms:
Electrical & Electronics
Verilog Digital System Design

Dewey Class. No.: 621.392 / NAV/V

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For support, contact our library staff:

Mr. Justine Thomas

Librarian (Gr. I)

Email: librarian@sjcetpalai.ac.in

Phone: +91 94476 94464

Mr. Centil Jose

Librarian (Gr. II)

Phone: +91 94964 64673

Mr. Geo Mathew

Librarian (Gr. III)

Phone: +91 94477 63627

Mr. Sibin Sebastian

Librarian (Gr. III)

Email: sibin.sebastian@sjcetpalai.ac.in

Phone: +91 88934 36127

Library Contact:
Email: librarian@sjcetpalai.ac.in, justine@sjcetpalai.ac.in
Address: Librarian, Library & Information Division,
St. Joseph’s College of Engineering & Technology, Palai, Choondacherry PO, Plassanal (Via), Kottayam PIN – 686 579, Kerala.
Phone: 04822 – 239 825 (Ext. 825)
Mobile: +91 94476 94464

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